IEEE Quantum Week 2026 Workshops

I spoke at two workshops during IEEE Quantum Week 2026 in Toronto:

• Quantum Engineering Cycle: Opportunities & Challenges on September 15, where I gave “Co-Designing Neutral-Atom Quantum Computers”.
• Quantum Accelerated Supercomputing on September 16, where I gave “From QPUs to Quantum Supercomputers”.

Both workshops addressed the engineering work required to turn quantum computing into useful, integrated systems. I contributed perspectives from Pasqal’s work on quantum software, middleware, and quantum-centric HPC.

Coverage

Quantum Zeitgeist covered both presentations in its QCE26 series on October 20, 2026:

• Quantum HPC integration at QCE26 became a question of shared words discusses my presentation on QRMI, scheduler integration, and on-premises usability.
• Quantum chemistry at QCE26 chased a shrinking knot covers my presentation of Pasqal’s collaborative magnetic-material simulation work.

Abstract: Co-Designing Neutral-Atom Quantum Computers

As quantum computing matures, the central challenge is no longer only improving individual devices, but making quantum systems usable within larger hybrid computing workflows.

In this talk, we present recent progress at Pasqal towards full-stack neutral-atom quantum computing, with the engineering-cycle perspective suggested by the workshop. We discuss how software and systems layers help translate hardware capabilities into usable computational resources. Particular emphasis will be placed on the interfaces between device constraints and higher-level execution: how noise, calibration overhead, control limitations, and application requirements shape the design and deployment of practical quantum workflows.

We illustrate this approach through recent hardware and application advances: the use of 256 qubits for quantum simulation of a real material, and the demonstration of an end-to-end logical quantum algorithm deployed on a neutral-atom QPU. These examples highlight how in-depth analysis of algorithm requirements and performance informed hardware development, and vice versa.

Together, they support a methodology in which modelling, control, software, and application performance are tightly and scalably integrated.